(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing stacked gates, and more particularly, to a method of fabricating memory devices employing stacked gates having an improved interpoly dielectric layer.
(2) Description of the Prior Art
One class of semiconductor memory devices employs floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. A Flash EEPROM is a device in which the entire array, or a large subset, of the memory cells can be erased simultaneously. A stacked gate Flash EEPROM device has a floating gate which is isolated from the channel and source/drain regions by an insulating layer. An interpoly dielectric layer is formed overlying the floating gate to isolate it from the overlying control gate.
Negative voltage biasing and negative constant current stressing in present Flash memory devices give deleterious results. The major cause of these unfavorable behaviors is the rough surface presented by the floating polysilicon layer of the floating gate. Because of unfavorable surface conditions, a tremendous number of interfacial sites can be generated at the local interface between the bottom oxide layer of the ONO interpoly dielectric stack and the floating polysilicon. These trapping/detrapping sites contribute to the degradation of the integrity of the Flash device. The rough surface of the floating polysilicon can also aggravate the surface condition of the nitride layer of the ONO stack. Therefore, a second imperfect interface results between the silicon nitride layer and the top oxide layer of the ONO stack. The rough surface of the floating polysilicon layer can also result in the formation of convex edges at the top polysilicon layer. These edges can intensify any electrical fields that are present.
U.S. Pat. Nos. 5,625,213 and 5,457,061 to Hong et al show a method of fabricating a Flash EEPROM stacked gate structure wherein the interpoly dielectric layer is formed over the polysilicon layer and both are patterned to form the floating gate. U.S. Pat. No. 5,619,502 to Chang et al teaches forming an ONO interpoly dielectric layer in which the nitride layer is thinner than either of the sandwiching oxide layers.